1. Field of the Invention
The present invention relates to a semiconductor device transporting and handling apparatus (commonly called IC handler) which is suitable for use, in an IC testing apparatus (commonly called IC tester) for testing semiconductor devices such as semiconductor integrated circuit elements (hereinafter referred to as IC) typical of the semiconductor devices, for transporting ICs to a testing section, carrying the tested ICs out of the testing section and sorting them out. More particularly, the present invention relates to a semiconductor device transporting and handling apparatus which is capable of exposing semiconductor devices to an atmosphere of a predetermined temperature for a sufficiently long time prior to subjecting them to the testing.
2. Description of the Related Art
FIG. 6 illustrates the general construction of one example of the prior semiconductor device transporting and handling apparatus (hereinafter referred to as IC handler) called "horizontal transporting system". A plurality of tray groups denoted generally by the reference numeral 2 are disposed on a frame or platform 1 constituting a base along the lower side 1A thereof as viewed in the drawing. Each tray in the tray groups 2 is adapted to be loaded with ICs as the case may be. Each of the tray groups 2A-2E consists of a number of trays vertically stacked one on another. The leftmost tray group 2A as viewed in the drawing is positioned at a loader section. The trays of the group 2A in the loader section are loaded with ICs undergoing a test hereafter (ICs to be tested).
A carrier arm 3 picks up one IC at a time, in this example, from the uppermost tray of the stacked tray group 2A and transports it onto a turntable 4 called "soak stage". A row of positioning recesses 5 for defining the positions for receiving the ICs are formed in the turntable 4 at equal angular intervals on a concentric circle. Each positioning recess 5 is of substantially square shape and is surrounded on four sides by upwardly inclined walls. Each time the turntable 4 rotates by one pitch in a clockwise direction in the illustrated example, the carrier arm 3 drops one IC down into one of the positioning recesses 5.
The reference numeral 6 denotes a contact arm for transferring the ICs conveyed by the turntable 4 one by one to a testing section 7. Specifically, the contact arm 6 is adapted to pick up by vacuum suction an IC from each of the positioning recesses 5 in the turntable 4 and transports it to the testing section 7. The contact arm 6 has three arms and performs the operations, by rotation of the three arms, of sequentially transferring the ICs to the testing section 7 and of sequentially transferring the ICs tested in the testing section 7 to a transfer arm 8 located at an exit from the testing section. It should be noted that the turntable 4, the contact arm 6 and the testing section 7 are contained in a constant temperature chamber or thermostatic chamber 9 so that ICs to be tested may undergo the testing within the chamber 9 while being maintained at a predetermined temperature. The interior of the constant temperature chamber 9 is temperature controlled so as to be maintained at a preset high or low temperature to apply a predetermined temperature stress to ICs to be tested.
ICs taken out of the constant temperature chamber 9 by the transfer arm 8 located at the exit of the chamber are sorted out on the basis of the test results and stored in corresponding one of the three tray groups 2C, 2D and 2E in this example located in an unloader section. For example, non-conforming or bad ICs (ICs having a defect or failure) are stored in a tray of the rightmost tray group 2E, conforming or good ICs (ICs having no defect or failure) are stored in a tray of the tray group 2D at the left side of the tray group 2E, and ICs which have been determined to need a retest are stored in a tray of the tray group 2C at the left side of the tray group 2D. This sorting is performed by carrier arms 10 and 11.
The tray group 2B located at the second position from the leftmost side is an empty tray group located at a buffer section for accommodating trays emptied of ICs in the loader section. When the uppermost tray of any one of the tray stacks of the tray groups 2C, 2D and 2E in the unloader section is filled with ICs, a tray of this empty tray group 2B is conveyed to the top of the corresponding tray stack to be used to store ICs therein.
While in the IC handler illustrated in FIG. 6 the turntable 4 has only one row of positioning recesses 5 spaced at equal angular intervals for defining the positions for receiving the ICs formed therein on a concentric circle such that each time the turntable 4 rotates by one pitch in a clockwise direction the carrier arm 3 deposits one IC into one of the positioning recesses 5, another type of IC handler as shown in FIG. 7 is also in practical use in which the turntable 4 has two rows of angularly equally spaced apart positioning recesses 5 formed therein on concentric circles. The arrangement in the latter case is such that the carrier arm 3 transports two ICs to be tested at a time from a tray located in the loader section and deposits the two ICs into corresponding two of the positioning recesses 5 of the two rows with each incremental (one pitch) rotation of the turntable 4. The IC handler shown in FIG. 7 is identical to that shown in FIG. 6 except that the contact arm 6, the transfer arm 8 at the exit side and the carrier arm 10 are adapted to handle two ICs at a time and that the testing section 7 is also configured to conduct examination on two ICs at a time. Accordingly, the corresponding parts of the FIG. 7 configuration are indicated by the same reference numerals and will not be further described.
It should be pointed out here that in the IC handler shown in FIG. 6, an IC to be tested is deposited on the turntable 4 at an angular position (A) by the carrier arm 3 and delivered from the turntable 4 at an angular position (B) to the testing section 7 by the contact arm 6. While being carried by the turntable 4 through about 240.degree. from the position (A) to the position (B), the IC is heated (or cooled) to the temperature in the constant temperature chamber 9.
Typically, since positioning recesses 5 are formed in the turntable 4 with a pitch (angular interval) of about 12.degree. on a concentric circle, there are twenty positioning recesses 5 arrayed within the angular extent of 240.degree.. It is to be noted that the time required for the IC to undergo the test in the testing section 7 is comparatively short, say, of the order of a few seconds. If the turntable 4 is rotated in synchronism with the testing period in the testing section 7, relatively large size ICs may not reach the designed temperature in the constant temperature chamber 9 within the time during which they are moved from the angular positions (A) to (B), due to the short distance of travel between the two positions (A) and (B). For this reason, despite the fact that the test in the testing section 7 has been completed, there may have to be a waiting time until the ICs to be tested next are heated (or cooled) to a predetermined temperature, resulting in an undesirable increase in the time required for the testing.
Likewise, with the IC handler shown in FIG. 7, an IC to be tested is deposited on the turntable 4 at an angular position (A) and delivered from the turntable 4 at an angular position (B) to the testing section 7, during which the IC is carried by the turntable 4 through about 240.degree.. Since two rows of positioning recesses 5 lying on concentric circles in the turntable 4 are also arranged with a pitch of about 12.degree., there are twenty positioning recesses 5 within the angular extent 240.degree.. Consequently, as is the case with the IC handler shown in FIG. 6, relatively large size ICs may not reach the designed temperature within the time during which they are moved from the angular positions (A) to (B), because of the distance of travel between the two positions (A) and (B) being too short, so that notwithstanding the test in the testing section 7 having been completed, a wait may be required until the ICs to be tested next are heated (or cooled) to a predetermined temperature, resulting in an undesirably elongated time required for the testing.